Motivation and Concept

tern generation (ATPG) has yielded effective solutions for combinational circuits, developing efficient methods for sequential circuits remains difficult. The difficulty results because state and time frame expansion has caused a virtual explosion of the relevant search space. The commonly used branch-and-bound technique1 is infeasible for large sequential circuits because of the exponentially growing numbers of backtracks. In recent years, researchers have focused on simulation-based techniques2-7 because of their scalability to large circuits. We divide this class of test generators into fault simulation based4,6,7 and logic simulation based.2,5 In the former, a test generator repeats fault simulation runs to gather information on targeted faults to guide the test generator’s search for test sequences. In the latter, logic simulation makes up the bulk of computation, with minimal calls to fault simulation. Logic-simulation-based test generators usually target a property of the fault-free circuit and try to derive a sequence that exercises this property to a large extent. In research by Saab and colleagues,2 the test generator tries to maximize the circuit activity (events in logic simulation), whereas in research by Pomeranz and Reddy5 the test generator aims to maximize the number of new states visited. Recently, researchers have combined fault-simulation and circuit properties6,7 in cases where static test-set compaction yields the embedded properties. For example, compaction can identify useful vectors that can be repeated to detect additional faults;6 moreover, spectral properties embedded in the circuit under test can be extracted to assist generation of test vectors.7 Generally, because logic simulation is significantly less complex than fault simulation, execution time can be far shorter. However, the fault coverage of logic-simulation-based test generators, such as Cris2 and Locstep,5 can be inferior for large circuits when compared with that of fault-simulation-based, state-of-the-art test generators such as Strategate,4 Proptest,6 and Spect.7 In this article, we present an efficient logicsimulation-based test generator that executes significantly more quickly than its fault-simulationbased counterparts. This test generator’s fault coverage compares favorably with that of the latest techniques for large sequential circuits.